The present disclosure relates generally to memory devices and, more particularly, to data security techniques for protecting data stored in the memory devices.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present techniques, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
In general, a computing system may include an electronic device that, in operation, communicates information via electrical signals. For example, a computing system may include a processor communicatively coupled to a memory device, such as a dynamic random-access memory (DRAM) device employed on a dual in-line memory module (DIMM). In this manner, the processor may communicate with the memory device, for example, to retrieve executable instructions, retrieve data to be processed by the processor, and/or store data output from the processor.
During use, these electrical signals may be accessed, for example, for execution of commands or to facilitate a computer operation. The DRAM device associated with many memory systems may be a security vulnerability, where unpermitted, unauthorized, or malicious users may attempt to access sensitive data stored within the DRAM device. To facilitate improving data security of the DRAM device, reactionary processes may be performed in response to detection of an unauthorized DRAM device access, for example, by a memory controller wiping data stored in the DRAM device (e.g., body biasing during a power ramp), overwriting data stored in the DRAM device (e.g., using word-line coupling techniques, row-copy techniques), or the like. These methods, however, are time-intensive, resource-intensive, and susceptible to internal capacitances of the DRAM device that may continue to store data even after power is removed from the DRAM device. In addition, attempting to erase the data using body biasing techniques may use detection of a power-on state, which may be unstable or generally unrealistic.